NANOPACK

Nano packaging technology for interconnect and heat dissipation

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One of the major limitations to the continuous growth of the semiconductor and power electronics industries is the lack of integration density and thermal management solutions. Transistor downscaling is quickly reaching its limits, forcing a new focus on heterogeneous integration and 3D packaging, in order to further push performance and density. Improved thermal management solutions will have a strong impact on energy and manufacturing efficiencies, as well as on component reliability.

NANOPACK is a FP7 European large-scale integrating project aiming at the development of new technologies and materials for low thermal resistance interfaces and electrical interconnects. NANOPACK explores the capabilities offered by nanotechnologies (such as carbon nanotubes, nanoparticles and nano-structured surfaces) and by using different mechanisms to enhance interparticle contact formation, compatible with high-volume manufacturing technologies.

Three parallel approaches are pursued by NANOPACK to achieve the required thermal and electrical performances: enhancement of bulk conductivity of filled systems, reduction of Bond Line Thickness (BLT), and optimisation of nano-scale thermal and electrical contact surfaces.

Conventional Thermal Interface Materials (TIM), such as grease, adhesive or phase change materials, are currently developed and optimised in the project. More than 10W/mK of thermal conductivity has been reached by tri-modal thermal grease, with spherical metallic micro-spheres and graphitised carbon nano-fibres in silicone matrix. Bimodal electrically conductive adhesive with 10W/mK of thermal conductivity has been fabricated by incorporating silver flakes and micro silver spheres in heat-resistant flexibilised bi-epoxy matrix.

New types of materials and technologies have also been developed, targeting much higher thermal performances than conventional ones. Thus, a specific process has been established to manufacture a metal-polymer composite, based on polyimide fibres network infiltrated with metal alloy. Two generations of this material exhibit respectively 19 and 48W/mK of effective thermal conductivity. Thanks to their extremely high thermal properties, carbon nanotubes vertically oriented and infiltrated by a polymer matrix represent a very promising technology for future thermal interfaces and are under investigation by NANOPACK within the project.

The thickness control of the thermal interfaces is also a critical feature of the heat dissipation path. A surface modification technique based on micro-machined Hierarchical Nested Channels (HNC) has proven its efficiency to reduce the final BLT by >50% for the majority of TIMs on 1-250cm2 interfaces. It also allows reduction of the squeezing time during interface assembly. Advanced surface modifications at nano-scale such as gold nano-sponges surface enhancement technique is also under evaluation to decrease interfacial contact resistance.

Fine-pitch CNT bumps reported with isotropic adhesives are serious candidates as future flip chip interconnect technology.

In addition, specific works are carried out by NANOPACK to build accurate test benches dedicated to the thermal and electrical measurements of thin and highly conductive layers. All these activities are also supported by high-end modelling and simulations using molecular dynamics, FDTD and analytics methods.

The benefits of these technologies will be evaluated in different applications to demonstrate improved performance of microprocessors, automotive and aerospace high-power electronics and radio-frequency switches.

NANOPACK fills several gaps reported by the ITRS roadmap and covers several ENIAC strategic research agenda focus topics in the heterogeneous integration area.

The NANOPACK consortium comprises 14 partners, representing eight European countries. Major industrial companies: Bosch (Germany), IBM (Switzerland), Thales Aerospace (France) and Thales Research & Technology (France); Innovative SMEs: FOAB Elektronik (Sweden), MicReD Mentor Graphics (Hungary), Electrovac (Austria), Berliner Nanotest und Design (Germany); academic groups: Budapest University of Technology & Economics (Hungary), Fraunhofer Insititut IZM (Germany), Chalmers University of Technology (Sweden), Catalan Institute of Nanotechnology (Spain), VTT Micro and Nanoelectronics (Finland), Institut d’Electronique de Microtechnologies et de Nanotechnologie (France).

The NANOPACK consortium gratefully acknowledges the financial support of the European Community through the Seventh Framework Programme (FP7/2007-2013) grant agreement n°216176.

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